Internship in the Field of VLSI and Semiconductors
Team Members: MEHTA ZENIL SANATBHAI
Guided by: Prof. Sardhara Ravin Nathalal(ravin.sardhara.ec@vvpedulink.ac.in)
The primary objective of my microchip-design internship was to translate theoretical VLSI concepts into hands-on expertise. I set out to understand each stage of the integrated-circuit design flow—from interpreting design specifications through logic and circuit design to physical implementation and verification—and to apply this knowledge by actively designing and testing digital blocks. By engaging with real-world tools and workflows, I aimed to develop a comprehensive, practice-oriented skill set that prepares me for future roles in advanced VLSI and semiconductor design.
Internship in the Field of VLSI and Semiconductors
Team Members: SACHDEV DEV RUPESHBHAI
Guided by: Prof. Sardhara Ravin Nathalal(ravin.sardhara.ec@vvpedulink.ac.in)
The objective of the industrial training at Einfochips, an Arrow company, was to build a strong foundation in system-level programming and professional development. This included gaining proficiency in Linux fundamentals, shells scripting, and advanced C programming using industry-recognized resources. Additionally, the program aimed to enhance understanding of data structures and foster personal growth through self-reflection assessments and quality management sessions, ultimately preparing trainees for efficient project execution in a collaborative digital workspace.
Instrumentation in Thermal Power Plant
Team Members: BHADOURIA MANSI MANOJKUMAR
Guided by: Prof. Sardhara Ravin Nathalal(ravin.sardhara.ec@vvpedulink.ac.in)
The objective of internship at Sikka Thermal Power Plant was to understand the critical role of Instrumentation and Control in monitoring and managing key parameters such as temperature, pressure, and level in large-scale thermal power operations. The internship aimed to provide practical insights into how instrumentation ensures the efficient and safe functioning of various power plant cycles.
Asynchronous FIFO Using Verilog
Team Members: JOSHI GAUTAM SHIVDAYALBHAI
Guided by: Prof. Sardhara Ravin Nathalal(ravin.sardhara.ec@vvpedulink.ac.in)
This project focuses on the design and implementation of an Asynchronous FIFO (First-In-First-Out) memory buffer using Verilog HDL. Asynchronous FIFOs are widely used for data transfer between two systems operating at different clock domains. The design ensures reliable data storage and retrieval while addressing challenges like metastability, data overflow, and underflow. Key components such as dual-port memory, read/write pointers, and gray code synchronization are implemented to maintain data integrity. The project demonstrates an efficient and robust FIFO architecture suitable for high-speed digital systems and embedded applications.
Design of DMA memory Controller
Team Members: JOSHI STUTI HARSHADBHAI
Guided by: Prof. Sardhara Ravin Nathalal(ravin.sardhara.ec@vvpedulink.ac.in)
This project presents the design and implementation of a Direct Memory Access (DMA) controller using Verilog HDL. The DMA controller enables efficient data transfer between memory and peripherals without continuous CPU intervention, thus improving overall system performance. The design includes key components such as address generation, data counters, control logic, and handshake mechanisms. By supporting burst transfers and multiple modes of operation, the DMA controller is optimized for high-speed and low-latency communication in embedded and SoC systems.
Implementation and Verification of APB Protocol
Team Members: JOSHI GAUTAM SHIVDAYALBHAI
Guided by: Dr. Jignesh Joshi(jignesh.joshi.ec@vvpedulink.ac.in)
This project involves the design and functional verification of the Advanced Peripheral Bus (APB) protocol using Verilog HDL. APB, a part of the AMBA bus family, is widely used for low-power and low-bandwidth communication with peripherals. The implementation includes APB master and slave modules, supporting read and write operations as per protocol specifications. Verification is carried out using testbenches to ensure correct timing, data transfer, and control signal behavior. The project demonstrates a reliable and efficient APB interface suitable for integration into ARM-based SoC designs.
Internship in the Field of VLSI Verification
Team Members: Bhatt Prerak Jitendrabhai
Guided by: Dr. Vishal Nimavat(vishal.nimavat.ec@vvpedulink.ac.in)
This project explores the growing complexity of modern SoC (System on Chip) design in the era of compact and cost-effective hardware driven by advancements in semiconductor technology. To manage this complexity, automation through scripting and efficient verification methods is essential. The project focuses on frontend design using Verilog HDL and advances into functional verification using System Verilog. It highlights the importance of achieving near 100% functional coverage and the role of automation using scripting languages like Shell in streamlining tool usage, ultimately aiming for efficient and reliable chip design and verification.
Multi Million Gates Implementation in Design for Testability or ASIC Implementation on SoC using 28nm and 16nm Technology
Team Members: Dudhatra Vrutik Dilipbhai
Guided by: Dr. Jignesh Joshi(jignesh.joshi.ec@vvpedulink.ac.in)
This project focuses on the implementation of multi-million gate designs in the context of Design for Testability (DFT) and ASIC development on System-on-Chip (SoC) platforms using advanced 28nm and 16nm process technologies. It addresses challenges associated with increasing design complexity, such as scan insertion, test coverage optimization, and timing closure. The project emphasizes the integration of DFT techniques to ensure testability without compromising performance, power, or area. Through this work, efficient methodologies for handling large-scale ASIC implementations at cutting-edge technology nodes are explored and applied.
Internship in the Field of Chip Design
Team Members: Kyada Keshviben Bhupatbhai
Guided by: Dr. Sneha Pandya(sneha.pandya.ec@vvpedulink.ac.in)
This project focuses on the design and development of a VLSI (Very Large Scale Integration) chip, covering the complete front-end flow from specification to synthesis. Key aspects such as design optimization, timing analysis, and area efficiency are addressed to ensure high-performance outcomes. The project provides hands-on experience in digital IC design and lays a strong foundation for working with ASIC or FPGA-based systems in advanced semiconductor technologies.